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www.gennum.com GS9074A hd-linx? ii adaptive cable equalizer GS9074A data sheet 34166 - 3 march 2006 1 of 16 features ? smpte 259m compliant ? automatic cable equalization ? multi-standard operation from 143mb/s to 360mb/s ? supports dvb-asi at 270mb/s ? small footprint (4mm x 4mm) ? pb-free and rohs compliant ? manual bypass (useful for low data rates with slow rise/fall times) ? performance optimized for 270mb/s ? typical maximum equalized length of belden 1694a cable: 350m at 270mb/s ?50 differential output (with internal 50 pull-ups) ? manual output mute or programmable mute based on max cable length adjust ? single 3.3v power supply operation ? operating temperature range: 0c to +70c applications ? smpte 259m coaxial cable serial digital interfaces. description the GS9074A is a second-generation high-speed bicmos integrated circuit designed to equalize and restore signals received over 75 co-axial cable . the GS9074A is designed to support smpte 259m, and is optimized for performance at 270mb/s. the GS9074A features dc restoration to compensate for the dc content of smpte pathological test patterns. a voltage programmable mute threshold (mcladj) is included to allow muting of the GS9074A output when an approximate selected cabl e length is reached for smpte 259m signals. this feature allows the GS9074A to distinguish between low amplitude sd-sdi signals and noise at the input of the device. the serial digital outputs of the GS9074A may be forced to a mute state by applying a voltage to the mute pin. power consumption is typically 215mw using a 3.3v power supply. the GS9074A is lead-free, and the encapsulation compound does not contain halogenated flame retardant (rohs compliant). functional block diagram cable length adjustor carrier detect mute equalizer dc restore output agc cd mute sdo bypass sdo sdi sdi mcladj
GS9074A data sheet 34166 - 3 march 2006 2 of 16 contents features ....................................................................................................................... .1 applications................................................................................................................... 1 description .................................................................................................................... 1 1. pin out ..................................................................................................................... .3 1.1 GS9074A pin assignment ... .............. .............. .............. .............. ........... ........3 1.2 GS9074A pin descriptions .. .............. .............. .............. .............. ........... ........3 2. electrical characteristics ...........................................................................................5 2.1 absolute maximum ratings ............................................................................5 2.2 dc electrical characteristics ............... ...........................................................5 2.3 ac electrical characteristics .............. .............................................................6 2.4 solder reflow profiles .....................................................................................7 3. input / output circuits ............................... ................................................................9 4. detailed description .................................. ..............................................................11 4.1 serial digital inputs .......................................................................................11 4.2 cable equalization ......... .............. .............. .............. .............. .............. .........11 4.3 programmable mute output ..........................................................................12 4.4 mute and carrier detect ................................................................................12 5. application information............................................................................................13 5.1 typical application circuit .............................................................................13 6. package & ordering information .............................................................................14 6.1 package dimensions ....................................................................................14 6.2 recommended pcb footprint ............. .............. ............ ........... ........... .........15 6.3 packaging data .............................................................................................15 6.4 ordering information .....................................................................................15 7. revision history ......................................................................................................16
GS9074A data sheet 34166 - 3 march 2006 3 of 16 1. pin out 1.1 GS9074A pin assignment figure 1-1: 16-pin qfn 1.2 GS9074A pin descriptions GS9074A (top view) 1 v ee _a v ee _a sdi sdi 2 3 4 sdo sdo v ee _d v ee _d 12 11 10 9 agc agc bypass mcladj 5 7 68 v cc _a mute cd v cc _d 13 14 15 16 center pad (bottom of package, internally bonded to vee_a) table 1-1: GS9074A pin descriptions pin number name timing type description 1, 4 vee_a analog power most negative power supply for analog circuitry. connect to gnd. 2, 3 sdi, sdi analog input serial digital differential input. 5, 6 agc, agc analog ? external agc capacitors. (see section 5.1 typica l application circuit.) 7 bypass not synchronous input forces the equalizing and dc re store stages into bypass mode when high. no equalization occurs in this mode. 8 mcladj analog input maximum cable length adjust. adjusts the approximate maximum amount of cable to be equalized (from 0m to the maximum cable length). the output is muted (latched to the last state) when the maxi mum cable length is achieved. note: mcladj is only recommended for data rates up to 270mb/s. 9 vee_d analog power most negative power supply for the digital circuitry and output buffer. connect to gnd. 10, 11 sdo , sdo analog output equalized serial digital differential output.
GS9074A data sheet 34166 - 3 march 2006 4 of 16 12 vee_d analog power most negative power supply for the digital circuitry and output buffer. connect to gnd. 13 vcc_d analog power most positive power supply for the digital i/o pins of the device. connect to +3.3v dc. 14 mute not synchronous input control signal input levels are lvcmos/lvttl compatible. (3.3v tolerant) (internal pull down resistor) when the mute pin is set high by t he application interface, the serial digital output of the device will be forced to a steady state. when the mute pin is set low, the se rial digital output of the device will be active. note: this pin may be connected directly to the cd pin to allow mute on loss of carrier. 15 cd not synchronous output status signal output signal levels are lvcmos/lvttl compatible. indicates the presence of a good input signal. when the cd pin is low, a good input signal has been detected. when this pin is high, the input signal is invalid. this pin will indicate loss of ca rrier for data rates > 19mb/s. 16 vcc_a analog power most positive power supply for the analog circuitry of the device. connect to +3.3v dc. ? center pad ? power internally bonded to vee_a. table 1-1: GS9074A pin descriptions (continued) pin number name timing type description
GS9074A data sheet 34166 - 3 march 2006 5 of 16 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics parameter value supply voltage -0.5v to +3.6 v dc input esd voltage 2kv storage temperature range -50c < t s < 125c input voltage range (any input) -0.3 to (v cc +0.3)v operating temperature range 0c to 70c reflow temperature 260c table 2-1: dc electrical characteristics v dd = 3.3v, t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units notes supply voltage v cc ? 3.135 3.3 3.465 v 5% power consumption p d t a = 25c ? 215 ? mw ? supply current i s t a = 25c ? 65 ? ma ? output common mode voltage v cmout t a = 25c ? v cc - v sdo /2 ? v ? input common mode voltage v cmin t a = 25c ? 1.75 ? v ? mcladj dc voltage (to mute signal) ?0m, t a = 25c ? 1.3 ? v ? mcladj range ? t a = 25c ? 0.4 ? v ? cd output voltage v cd (oh) carrier not present 2.4 ? ? v ? v cd (ol) carrier present ? ? 0.4 v ? mute input voltage required to force outputs to mute v mute min to mute 2.0 ? ? v ? mute input voltage required to force outputs active v mute max to activate ? ? 0.8 v ?
GS9074A data sheet 34166 - 3 march 2006 6 of 16 2.3 ac electrical characteristics table 2-2: ac electrical characteristics v dd = 3.3v, t a = 0c to 70c, unless otherwise shown parameter symbol conditions min typ max units notes serial input data rate dr sdo ? 143 ? 360 mb/s ? input voltage swing v sdi t a =25c, differential 720 800 950 mv p-p 1 output voltage swing v sdo 100 load, t a =25c, differential ? 750 ? mv p-p ? maximum equalized cable length ? 270mb/s, belden 1694a, 350m ?0.2? ui2 ? 270mb/s, belden 8281, 280m ?0.2? ui2 ? 360mb/s, belden 1694a, 190m ?0.25? ui 2 ? 360mb/s, belden 8281, 140m ?0.25? ui 2 output rise/fall time ? 20% - 80% ? 80 220 ps ? mismatch in rise/fall time ? ? ? ? 30 ps ? duty cycle distortion ? ? ? ? 100 ps ? overshoot ? ? ? ? 10 % ? input return loss ? ? 15 ? ? db ? input resistance ? single ended ? 1.64 ? k ? input capacitance ? single ended ? 1 ? pf ? output resistance ? single ended ? 50 ? ? notes: 1. 0m cable length. 2. equalizer pathological.
GS9074A data sheet 34166 - 3 march 2006 7 of 16 2.4 solder reflow profiles the device is manufactured with matte-sn te rminations and is compatible with both standard eutectic and pb-free solder re flow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 2-1 . the recommended standard eutectic reflow profile is shown in figure 2-2 . figure 2-1: maximum pb-free solder reflow profile (preferred) figure 2-2: standard eutectic solder reflow profile (pb-free package) 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
GS9074A data sheet 34166 - 3 march 2006 8 of 16 figure 2-3: test circuit gigabert 1400 ext. clock clock out data out ext. clock 1.485ghz/270mhz gs1574a/9074a test board tds 820 ch. 1 ch. 2 out in out ext. trigger 50/75 8281 or 1694a cable
GS9074A data sheet 34166 - 3 march 2006 9 of 16 3. input / output circuits figure 3-1: input equivalent circuit figure 3-2: mcladj equivalent circuit figure 3-3: output circuit 3k 3.6k 3k 3.6k rc sdi sdi v cc mcladj 12.2k 150 + - 50 50 sdo sdo
GS9074A data sheet 34166 - 3 march 2006 10 of 16 figure 3-4: mute and bypass circuits figure 3-5: cd circuit mute, bypass cd
GS9074A data sheet 34166 - 3 march 2006 11 of 16 4. detailed description the GS9074A is a high speed bicmos ic designed to equalize serial digital signals. the GS9074A can equalize sd serial digital signals, and will typically equalize greater than 350m at 270mb/s. the GS9074A is powered from a single +3.3v power supply and consumes approximately 215mw of power. 4.1 serial digital inputs the serial data signal may be con nected to the input pins (sdi/sdi ) in either a differential or single ended configurat ion. ac coupling of the inputs is recommended, as the sdi and sdi inputs are internally biased at approximately 1.8v. 4.2 cable equalization the input signal passes through a variabl e gain equalizing stage whose frequency response closely matches the inverse of th e cable loss characteristic. in addition, the variation of the frequency response with control voltage imit ates the variation of the inverse cable loss char acteristic with cable length. the edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. this error signal is integrated by both an internal and an external agc filter capa citor providing a steady control voltage for the gain stage. as the frequency response of the gain stage is automatically varied by the application of negative feedback, th e edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. the equalized signal is also dc restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to ac coupling. the digital output signals have a nominal voltage of 750mv pp differential, or 375mv pp single ended when terminated with 50 as shown in figure 4-1 .
GS9074A data sheet 34166 - 3 march 2006 12 of 16 figure 4-1: typical output voltage levels 4.3 programmable mute output the GS9074A incorporates a programmable threshold output mute (mcladj). in applications where ther e are multiple input channels using the GS9074A, it is advantageous to have a programmable mute output to avoid signal crosstalk. the output of the GS9074A can be muted when the input signal decreases below a certain input level. this threshold is determined using the input voltage applied to the mcladj pin. the mcladj pin may be left unconnected for applications where output muting is not required. this feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. the use of a carrier detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. note: mcladj is only recommended for data rates up to 360mb/s. 4.4 mute and carrier detect the GS9074A includes a mute input pin that allows the application interface to mute the serial digital output at any time . set the mute pin high to mute sdo and sdo . in this case, the outputs will mute regardless of the setting of the bypass pin. a carrier detect output pin (cd ) indicates the presence of a valid signal at the input of the GS9074A. when cd is low, the device has detected a valid input on sdi and sdi . when cd is high, the device has not detected a valid input. note: cd will only detect loss of carrier fo r data rates great er than 19mb/s. the cd output pin may be connected directly to the mute input pin to enable automatic muting of the GS9074A when no valid input signal has been detected. note: if the maximum cable length is e xceeded and the device is not in bypass mode the gs1574a will not assert the cd pin even if a carrier is present. 50 50 sdo sdo +187.5mv -187.5mv v cm = 2.925v typical +187.5mv -187.5mv v cm = 2.925v typical
GS9074A data sheet 34166 - 3 march 2006 13 of 16 5. application information 5.1 typical application circuit figure 5-1: GS9074A typical application circuit GS9074A sdi cd sdi vee_d mute vcc_d agc bypass mcladj vee_a note: all resistors in ohms, capacitors in farads, and inductors in henrys, unless otherwise noted. vee_a agc vcc_a sdo sdo vee_d 10n 1 10n sdo 4u7 4u7 + + sdo cd mute vcc bypass mcladj 470n 6.2n 75 sdi 1u 75 1u 37r4 vcc 4 5 6 2 3 8 7 16 12 13 11 14 15 9 10 470n
GS9074A data sheet 34166 - 3 march 2006 14 of 16 6. package & ordering information 6.1 package dimensions 4.00+/-0.05 b 4.00+/-0.05 2x 2x 0.15 0.15 c c 0.10 c 16x 0.08 c seating plane 0.85+/-0.05 0.00-0.05 0.65/2 0.65 detail b scale:nts datum a or b terminal tip 0.20 ref datum b 0.65 16x 0.35+/-0.05 0.10 0.05 c a b c datum a 2.76+/-0.10 0.40+/-0.05 2.76+/-0.10 detail b center tab pin 1 area a c
GS9074A data sheet 34166 - 3 march 2006 15 of 16 6.2 recommended pcb footprint the center pad should be connected to the most negative power supply plane for analog circuitry in the device (vee_a) by a minimum of 5 vias. note: suggested dimensions only. final di mensions should conform to customer design rules and process optimizations. 6.3 packaging data 6.4 ordering information 0.35 0.55 2.76 3.70 2.76 3.70 note: all dimensions are in millimeters. 0.65 center pad parameter value package type 4mm x 4mm 16-pin qfn package drawing reference jedec m0220 moisture sensitivity level 3 junction to case thermal resistance, j-c 31.0c/w junction to air thermal resistance, j-a (at zero airflow) 43.8c/w psi 11.0c/w pb-free and rohs compliant yes part number package temperature range GS9074A GS9074Acne3 16-pin qfn 0c to 70c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2005 gennum corporation. all rights reserved. printed in canada. www.gennum.com GS9074A data sheet 34166 - 3 march 2006 16 16 of 16 document identification data sheet the product is in production. gennu m reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. 7. revision history version ecr pcn date changes and/or modifications a 135927 ? february 2005 new document. 0 136165 ? march 2005 converted to preliminary data sheet. updated typical application circuit. updated input/output circuits. updated ac and dc electrical characteristics. updated description of mute and cd functionality. correced minor typing errors. updated center pad dimensions on pcb footprint. 1 137888 ? september 2005 corrected process to bicmos. 2 138357 37278 november 2005 converted to data sheet. 3 139635 38695 march 2006 corrected pad standoff height and tolerances for pad width & package dimension. corrected pad shape.

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